The clock and data recovery system is widely applied in fields such as magnetic disk storage, wireless communication, and optical network communication, etc. FIG. 1 is a structural block diagram of a typical clock and data recovery system, including a phase discriminator 102, a frequency discriminator 104, a charge pump (optional) & filter 103, a voltage control oscillator (VCO) 105, a frequency divider 106, and a data recovery retimer 101.
The frequency discriminator 104 compares the clock signal outputted by the frequency divider 106 with the reference clock, the generated error signal generates a control voltage through the charge pump (optional) & filter 103 to enable the frequency of VCO 105 to oscillate around the preset working frequency range. Then the phase discriminator 102 compares the phase relationship of the input data and the VOC feedback clock, and when the input data and the phase of the feedback clock are locked, the data recovery retimer 101 restores the data so as to eliminate the jitter and distortion generated during data transmission. Under ideal situation, the effective edge of the clock shall be sampled in the middle of the data so as to achieve the best anti-noise ability, however, during the actual circuit implementation, due to non-ideal situations such as the upper and lower current sources of the charge pump do not match each other, various module devices of the loop mismatch, process errors, etc., the effective edge of the clock usually is not sampled in the middle of the data when the loop is locked. When the loop is locked, the clock and the data have a fixed phase difference which increases the bit error rate. The generation of such phase difference can be equivalent to the situation that there is an offset current source Ioffset inside the charge pump (optional) & filter 103, as shown in FIG. 1. With the change of the error signal and reference signal of the phase discriminator 102, this offset current source equivalently charges (or discharges) the filter, causing the control voltage of the VCO to increase (or decrease) and then the clock generated by the VCO deviates from the best sampling point.
In order to realize best sampling, usually a phase adjustment function needs to be added into the loop so as to adjust the phase of the clock or data being locked to achieve minimum bit error rate. Since the frequency of the clock is very high, usually phase adjustment is carried out in the data path, in which a common implementation method is to realize phase adjustment inside the phase discriminator, as shown in FIG. 2. FIG. 2 is a block diagram of a typical phase discriminator with Hogge structure and phase adjustment function. The data are outputted as Q1 after being triggered by the down edge of a D trigger 201, and at the same time, data after being delayed (DATA_D) is obtained after going through a delay unit D1 203 and a phase adjustment unit 204, two paths of signals of Q1 and DATA_D are fed into an XOR gate 205 to generate an error signal (ERROR) representing the phase relationship between the clock and data, in addition, Q1 signal is delayed by half of a clock period through a latch 202 to obtain a signal Q2, and Q1 and Q2 signals are fed into the XOR gate 206 to generate a reference signal (REFERENCE) related to data flip, and the error signal and reference signal are fed into the charge pump (optional) & filter 103 to obtain the control voltage of the VCO so as to control the clock phase outputted by the VCO. The phase adjustment unit 204 can directly delay the effective flip edge of the data so as to adjust the pulse width of the ERROR signal and thus achieving the phase adjustment of the output clock of the VCO.
Another phase adjustment method is proposed in U.S. patent Ser. No. 10/159,788. Since the fixed phase difference when being locked can be equivalent to the situation that there is an offset current source Ioffset in a filter 108 in FIG. 3, the concept of this patent is to insert at the filter a switch current source array controlled by phase adjustment (PHASE_ADJUST) [1:0] and PHASE_ADJUST [3:2] so as to counter the equivalent offset current source Ioffset. FIG. 3 is a modular block diagram of this patent, in which the wires of the frequency discrimination portion is ignored. In this patent, a current source array 300 and a current source array 350 are added at the VCO control voltage, i.e. at the filter 108, the equivalent offset current source Ioffset is countered by the current generated by the current source array 300 and/or current source array 350 by way of the selection of PHASE_ADJUST [1:0] and PHASE_ADJUST [3:2] so as to achieve best sampling. A defect of this patent lies in that: the switch array controlled by PHASE_ADJUST [1:0] and PHASE_ADJUST [3:2] is directly connected to the VCO control lines, and the noise generated by the switch and/or introduced externally is easily to be coupled into the key modules of the VCO via a parasitic capacitor or substrate, which makes the output clock phase of the VCO jitter. Another defect of this patent lies in that: the phase adjustment is discontinuous and depends upon how many switch arrays are used, on the one hand it makes the actual best sampling not easy to be realized, and on the other hand, more pin resources will be occupied if the precision requirement on phase adjustment is higher.